The present disclosure relates to a semiconductor structure and a method of fabricating the same. More particularly, the present disclosure relates to a dual damascene interconnect structure in which the via profile of the interconnect structure is controlled and a method of fabricating the same.
Generally, semiconductor devices include a plurality of circuits which form an integrated circuit fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum-based interconnects.
Within a typical dual damascene interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Typically, the metal vias are present beneath the metal lines and both features are embedded within a dielectric material.
Although methods of forming such dual damascene interconnect structures are known, further improvements are needed to provide interconnect structures that are highly reliable and dependable.